www.fa irchildsemi.com ? 2005 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 3/22/07 AN-5058 family frequently asked questions (faqs) summary the following questions are typical of fairchild?s serdes? application support team answers the serdes family. if you have a questi on not addressed here, please contact your local fairchild representative or email to interface@fairchildsemi.com . what is a serdes?? the serdes is a low-cost, ultra-low emi, very small device that allows large amounts of data to flow between points such as displays, cameras, and controllers. this is achieved through a parallel-to-serial (serializer) conversion at the source and serial-to-parallel (deserializer) conversion at the destination. why is a fairchild serdes? serial interface better than a parallel interface solution? ? significantly reduced emi over single-ended technology solutions. ? no power-up sequencing requi red. no change needed for controller software. ? functions well where single-ended, current-mode technology fails. ? can provide a greater than 25 to 4 wire reduction. ? can provide a greater than 50 to 7 wire reduction in bi- directional interfaces. ? can provide a lower-cost, more reliable interface solution. ? can reduce overall component count over existing lvcmos technology. ? can use less board space ove r lvcmos technologies.
AN-5058 application note ? 2005 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 3/22/07 2 what are the differences among the serdes? devices? each device in the fairchild serdes family has been designed for specific architectures as shown in table 1. table 1. serdes? family comparisons fin12ac fin24ac fin24c fin212ac fin224ac fin324c function serializer / deserializer serializer / deserializer serializer / deserializer serializer / deserializer serializer / deserializer serializer / deserializer number of bits 12 22 24 12 22 24 max frequency 40mhz 20mhz 20mhz 40mhz 26mhz 15mhz factory options (***contact factory) 26mhz 48mhz & 2.5x2.5 package higher frequency version dynamic current (serializer) 8.5ma @ 5mhz 9.5ma @ 5mhz 11ma @ 10mhz 9.5ma @ 5mhz 9ma @ 5mhz 4ma @ 5.44mhz vdda/s 2.5 to 3.3v 2.5 to 2.9v 2.5 to 2.9v 2.5 to 3.6v 2.5 to 3.3v 2.5 to 3.0v vddp 1.65 to 3.6v 1.65 to 3.6v 1.65 to 3.6v 1.65 to 3.6v 1.65 to 3.6v 1.6 to v dda/s read / write write write write write write read / write ideal application camera small lcd small lcd camera small lcd small lcd small lcd recommended interface rgb controller rgb controller / rgb controller controller / rgb / spi selectable lvcmos edge rates no no no yes yes yes selectable lvcmos pulse width no no no yes yes yes output state tri-st ate tri-state tri-state tri- state tri-state known-state external timing required yes yes yes yes yes no additional features multiple frequency range multiple frequency range multiple frequency range; ctl standard or high;pll divide by 2 or 3 multiple frequency range rt180 esd in kv 15 8 8 14 15 15 package bga, mlp bga, mlp bga, mlp bga, mlp bga, mlp bga, mlp modes 0-power down; 1- ckref 20mhz to 40mhz; 2-ckref 5mhz to 14mhz; 3-ckref 8mhz to 14mhz 0-power down; 1- ckref 2mhz to 5mhz; 2-ckref 5mhz to 15mhz; 3-ckref 10mhz to 20mhz 0-power down; 1- 4-bit control; 2-4- bit control latch; 3- 2-bit control 0-power down; 1- ckref 20mhz to 40mhz; 2-ckref 5mhz to 14mhz; 3-ckref 8mhz to 28mhz 0-power down; 1- ckref 2mhz to 5mhz; 2-ckref 5mhz to 15mhz; 3-ckref 10mhz to 26mhz master/slave; par/spi; strobe selection; reset/standby; slew control serdes? family similarities and features similarities across fin24ac, fin224ac, and fin224c ? same package ? same pinout ? same voltage range ? same voltage translation range ? same ctl drive new features ? rolled lvcmos deserializer edge rates ? more esd protection ? more wide ckp pulse width (fin224ac) ? less power (fin224ac)
AN-5058 application note ? 2005 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 3/22/07 3 implementation what distance can a serdes? drive? the distance that can be driven depends on the data rates involved, acceptable bit error rate, and the transmission medium. the maximum distance in ansi/tia/eia-644-a, the lvds standard, is 10 meters. this distance is entirely application dependent. should special transmission mediums be used? the serdes can be used w ith any typical differential transmission medium, including flex circuits, pc board, and cables. what impedance should the transmission cable/flex be? the transmission line should be 100 differential. is a termination resistor needed at the inputs to the deserializer? no. the 100 termination resistor is integrated into the deserializer, so an external resistor is not necessary for either clock or data lines. do trace lengths need to be matched? yes. trace lengths need to be matched like any bus architecture. however, since th e serializer and deserializer have a flow-through design (traces do not need to cross to connect devices), the effort to achieve this is minimal. are there pcb layout guidelines available? yes. this can be downloaded from the fairchild website or may be obtained from interface@fairchildsemi.com what is the typical common-mode voltage of the serdes?? typical common-mode voltage is approximately 700mv. are there actual gerber files available to download to simplify or as an example of design? yes, please contact fairchild interface group at interface@fairchildsemi.com . is there a special power-down sequence between serializer and deserializer? there is no required power-down sequence. is there a special power-up sequence between supplies for either a serializer or deserializer? there is no required power-up sequence for either serializer or deserializer. are there special settings or switches for the pll (s1, s2) on the fin24 serializer? no. the pll has a very wide range of operation. when is ctl? technology better than single- ended, current-mode technology? in applications where a tr ansmission line must be ac coupled or when dc line ba lancing is necessary, single- ended, current-mode technology is usually inadequate. lvds is superior because dc bias can be restored on the deserializer side of the solution by using only resistors. in addition, differential technologies offer better emi than single-ended technologies. how much is emi reduced using a serdes?? serdes provides ultra-low em i as compared to legacy single-ended technologies. the actual amount of emi reduction varies per application; however, fairchild?s emi lab has documented cases of greater than -106.1db reduction over legacy single-ended technologies. is there special grounding scheme required for serdes?? no special ground wire is required. the ground wire can be subject to interference, as with single-ended, current-mode technologies. how low is the power in power-down mode? the serdes device is specified to use less than 10a in power-down mode. are emi filters necessary on the serial link? many applications no longe r require emi filters. if additional filtering is required, fairchild suggests implementing a shielded flex of ribbon cable for the following reasons: ? saves space on the pcb. ? makes a solid ground between board assemblies (no ground bounce). ? sideband signals in flex, not through serdes, can radiate; shielding helps reduce this phenomenon. ? esd/emi arrays are expensive.
AN-5058 application note ? 2005 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 3/22/07 4 test and diagnostics bits 21 and 22 on the fin24a don?t seem to work on the deserializer. why? data input to pin 21 on the fin24a serializer is output from the deserializer on pin 23. data input to pin 22 on the fin24a serializer is output at the deserializer on pin 24. why does the serial clock appear intermittent? this is normal as a word boundary is embedded into the serial stream. please refer to the datasheet for a more in- depth description. when i examine either the serial data path or the serial clock path, the signal is distorted. why? using a 50 high-speed terminated oscilloscope with the probe ground to one side of an lvds signal forces the 1.0v bias to ground, resulting in a ve ry incorrect signal. use high- impedance probes or, alternatively, a board ground may be offset to accommodate the ground of an oscilloscope. contact a fairchild serdes repr esentative for assistance. how should the serial clock or data stream look? the clock or data stream is approximately a 225mv peak- to-peak, roughly square, wave differential signal at approximately 700mv bias with respect to ground. where is the ground for serdes? devices? all device grounds are connected to the ground slug, underneath the serdes device. care should be taken when designing the board containing the serdes so that the solder mask is pulled back from this slug. do s1 and s2 control the frequency range for the fin24? the fin24 has a set frequency range, where s1 and s2 control the directionality of data bits [21:24]. what does a typical implementation look like for an rgb interface? please see figure 1 for a typical implementation. where can i get more information on how to use a serdes? with more complex architectures, such as microcontroller interface or for a bi-directional configuration? contact your local fairch ild representative or at interface@fairchildsemi.com . vddp a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 nc a1 nc d3 f3 g3 g2 b1 vddp1 notes: 1. write-only interface. 2. assumes bga die on display. 3. /cs used to strobe sub-display data. 4. 5. pclk used for rgb mode pin numbers for bga package. . /cs pclk gpio /stby /res cksel main display pclk r,g,b [5:0] hsync vsync sd oe sub-display d a t a [ 7 : 0 ] d/c /cs reset p/s r/w 2 edge rate control option slew must be connected to vdds or gnd for low power. vddp vdds/a strb0 strb1 cntl[5] r/w m/s par/spi /stby /res cksel r,g,b[5:0] dp[17:0] hsync_d/c cntl[0] vsync cntl[1] oe cntl[3] sd cntl[2] reset cntl[4] vddp vdds/a wclk0 wclk1 dp[17:0] cntl[0] cntl[1] cntl[2] cntl[3] cntl[4] cntl[5] r/w m/s par/spi slew /res h vddp1 vdds/a vddp2 vdds/a cks+ cks- ds+ ds- cks+ cks- ds+ ds- d1 e1 g1 f1 g1 f1 d1 e1 a4 b4 d4:g6 c4 c3 a3 b3 a2 b2 a1 d3 f3 g3 g2 b1 e3 d2 c1 e3 d2 c1 c2 e2 f2 c2 e2 f2 baseband processor figure 1. fin324c rbg application example
AN-5058 application note ? 2005 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 3/22/07 5 related datasheets fin12ac fin12ac fin24ac fin24c fin224ac fin224c fin324c serdes? is a trademark of fairchild semiconductor corporation. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fa irchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as criti cal components in life support devices or systems without the express written approval of the preside nt of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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